This book discusses the Reduced Instruction Set Computer architecture, a technique to streamline instruction execution. Sometimes, RISC is said to stand for “Relegate Important Stuff to the Compiler,” since the compilation process is done offline, and then the code is run. The time penalty paid at compile time is paid back by faster code execution. RISC machines place more burdens on their compilers. The alternative to RISC is CISC – Complex Instruction Set Computer. An example would be the legacy Intel x86, IA-32 instruction set. RISC involves a series of architectural features to enhance the throughput of operations. RISC has become a mainstream architectural feature in modern processors.
Glossary and list of references is included.
The author developed and taught a RISC computer architecture course at Loyola University. He currently teaches Embedded Systems at the Johns Hopkins University.
Glossary and list of references is included.
The author developed and taught a RISC computer architecture course at Loyola University. He currently teaches Embedded Systems at the Johns Hopkins University.
